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Saravana Kumar M

Assistant Professor

Email : saravana.kumar[at]ece.iitr.ac.in
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Analog and Mixed Signal Integrated Circuit Design, Data converter design for Instrumentation applications and Wireless Transceivers, RF CMOS IC design

FromToDesignationOrganisation
Jan-2022PresentAssistant ProfessorIndian Institute of Technology Roorkee
July-2021Dec-2021Senior Project OfficerIndustrial Consultancy and Sponsored Research, IIT Madras
May-2019June-2021Project OfficerIndustrial Consultancy and Sponsored Research, IIT Madras
Jan-2014June-2014Project AssociateIndustrial Consultancy and Sponsored Research, IIT Madras
July-2011Dec-2013Analog Design EngineerAnalog Devices India Private Ltd., Bangalore
DegreeSubjectUniversityYear Studied
Doctor of PhilosophyAnalog and Mixed Signal Integrated Circuit DesignIndian Institute of Technology Madras2021
Master of TechnologyVLSI Design Tools and TechnologyIndian Institute of Technology Delhi2011
Bachelor of EngineeringElectronics and Communication EngineeringAnna University, Chennai2009

Membership Details
IEEE Member

TitleCourse CodeCourseSemester
VLSI Mixed Signal CircuitsECN-584M. TechJan-May 2022

Journal Publications

  • S. Pavan and S. Manivannan, “Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3121418.
  • S. Manivannan and S. Pavan, “A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth,” in IEEE Solid-State Circuits Letters, vol. 4, pp. 92-95, 2021, doi: 10.1109/LSSC.2021.3071965.
  • S. Manivannan and S. Pavan, “Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3778-3789, Nov. 2020, doi: 10.1109/TCSI.2020.3013006.
  • S. Manivannan and S. Pavan, “Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3207-3215, Oct. 2018, doi: 10.1109/TCSI.2018.2826443.

Conference Publications

  • S. Manivannan and S. Pavan, “A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR,” 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, pp. 1-4, doi: 10.1109/CICC.2018.8357089.
  • S. Manivannan and S. Pavan, “Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702763.S. Kumar and S. Chatterjee, “A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time Delta Sigma Modulator for Audio Applications,” 2012 25th International Conference on VLSI Design, 2012, pp. 51-56, doi: 10.1109/VLSID.2012.45.